The board
- Hours
- Full time
- Where
- New York
- Posted
- Sep 24
As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.
The Opportunity: 4 month work term, starting January 2027
Join the ASIC IP team and contribute to the design and verification of client protocol mapping IP used in Ciena's WaveLogic coherent engine chipsets. This role provides hands-on exposure to digital ASIC development, verification methodologies, prototype development, automation, and optical networking technologies.
What you'd do
- Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA-based validation.
- Collaborate with design and verification engineers on client subsystem and core development activities.
- Implement digital designs using SystemVerilog, Verilog, and VHDL.
- Verify digital designs using SystemVerilog and UVM methodologies.
- Develop and enhance prototype and development automation solutions.
- Apply communications standards knowledge, including IEEE 802.3, ITU, and OIF specifications, within development activities.
- Contribute to digital ASIC development projects through assigned engineering tasks.
- Education: Actively enrolled in a Bachelor’s degree program in Electrical Engineering or Computer Engineering
- Previous experience with ASIC or FPGA development, as well as knowledge of and experience using System Verilog, Verilog, VHDL and Python
- Strong verbal and technical writing skills
- Starts
- 2026-09-24