- Hours
- Full time
- Where
- SAN JOSE
- Posted
- Aug 28
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern. (local candidates will be considered)
Intern will be responsible for validating both system-level and electrical performance of internal silicon test chips.
The role includes debugging silicon issues in close collaboration with analog and digital design teams, and delivering high-quality characterization reports.
The intern will work cross-functionally to ensure product functionality, reliability, and successful deployment.
The candidate is expected to be strongly motivated by the prospect of driving system and electrical testing efforts for identifying silicon issues and being involved in debug efforts for the same.
Very good fundam…
- Starts
- 2026-08-28